DocumentCode
1593665
Title
Access Transistor Design and Optimization for 65/45nm High Performance SOI eDRAM
Author
Wang, G. ; Parries, P. ; Cheng, K. ; Amarnath, K. ; Cai, J. ; Freeman, G. ; Agnello, P. ; Iyer, S.S.
Author_Institution
IBM Semicond. R&D Center, Hopewell Junction, NY
fYear
2008
Firstpage
97
Lastpage
98
Abstract
A 65 nm prototype embedded DRAM macro on partially depleted SOI (PD-SOI) substrate capable of <2. 0ns latency and the enabling cell technology have been described previously [1,2]. In this paper, we focus on the cell design and optimization for best retention and performance which have been extended to the 45 nm node.
Keywords
DRAM chips; integrated circuit design; silicon-on-insulator; DRAM macro; access transistor design; floating body effect minimization; silicon-on-insulator; Capacitance; Delay; Design optimization; Dielectrics; Manufacturing; Prototypes; Random access memory; Substrates; Subthreshold current; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
978-1-4244-1614-1
Electronic_ISBN
1524-766X
Type
conf
DOI
10.1109/VTSA.2008.4530816
Filename
4530816
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