Title :
Automatic fault model/logic model generation for large scale ASIC circuits
Author :
Wu, David M. ; Dibrino, Mike
Author_Institution :
IBM Adv. Workstation Syst., Austin, TX, USA
Abstract :
The authors describe a technique that generates accurate fault models/logic model for large scale ASIC circuits automatically. A summary of the algorithm is given, and a circuit example is discussed
Keywords :
application specific integrated circuits; automatic test software; circuit analysis computing; fault diagnosis; integrated circuit testing; logic CAD; logic testing; accurate model generation; algorithm; automatic model generation; fault model generation; large scale ASIC; logic model generation; Application specific integrated circuits; Automatic logic units; Books; Circuit faults; Computer industry; Equations; Large-scale systems; Logic circuits; Multiplexing; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410809
