Enhanced Stress Proximity Technique with Recessed S/D to Improve Device Performance at 45nm and Beyond

Author

Tan, S.S. ; Fang, S. ; Yuan, J. ; Zhao, L. ; Lee, Y.M. ; Kim, J.J. ; Robinson, R. ; Yan, J. ; Park, J. ; Belyansky, M. ; Li, J. ; Stierstorfer, R. ; Kim, S.D. ; Rovedo, N. ; Shang, H. ; Ng, H. ; Li, Y. ; Sudijono, J. ; Quek, E. ; Chu, S. ; Divakaruni, R.

Author_Institution

Chartered Semicond. Manuf. Ltd., Singapore

fYear

2008

Firstpage

122

Lastpage

123

Abstract

A novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with recessed S/D (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. pFET performance with Ion of 520 uA/um at Ioff of InA/um was achieved with the low cost processes. With optimized eSPT, 15% improvement in ring delay has been demonstrated.

Keywords

field effect transistors; enhanced stress proximity technique; low cost processes; pFET; ring delay; stress proximity technique; CMOS technology; Costs; DSL; Delay; Germanium silicon alloys; Microelectronics; Semiconductor device manufacture; Silicon germanium; Stress; Surface-mount technology; Device performance; Recessed S/D; SPT; Stress; eSPT;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-1614-1

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2008.4530827

Filename

4530827