Reduction of layout variations with stress-compensated hybrid STI fills: a comprehensive analysis

Author

Städele, M. ; Ilicali, G. ; Landgraf, E. ; Goldbach, M. ; Finsterbusch, S. ; Lindolf, J. ; Radecker, J. ; Uhlig, B.

Author_Institution

Qimonda AG, Neubiberg

fYear

2008

Firstpage

130

Lastpage

131

Abstract

Based on a detailed I-V analysis, 2D/3D process/device simulation, and inline wafer bow measurements, we have investigated a number of stress-induced layout effects on MOSFET performance caused by hybrid STI fills (HARP/HDP and SOG/HDP). Variations of active area dimensions, STI widths, and gate lengths were studied in 58 nm DRAM technology. Excellent STI-stress-related device performance variability (overall current and V_th variations smaller than 5% / 10 mV) is demonstrated with a proper choice of STI fill materials and adjusted layer thicknesses.

Keywords

MOSFET; stress effects; 2D/3D process/device simulation; DRAM technology; I-V analysis; MOSFET; inline wafer bow measurements; layout variations; overall current; size 58 nm; stress-compensated hybrid STI fills; stress-induced layout effects; Analytical models; Cause effect analysis; Compressive stress; MOSFET circuits; Performance analysis; Random access memory; Silicon compounds; Space technology; Stress measurement; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-1614-1

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2008.4530831

Filename

4530831