Automatic code generation for embedded systems: From UML specifications to VHDL code

The design of modern embedded systems becomes more complex every day, due to the increasing amount of components and distinct functionalities incorporated into a single system. To address this situation, projects´ abstraction level is continuously raised. In addition, techniques to speed up the code production process have emerged. These new trends lead to an important issue: the development of a consistent engineering process for systems co-design, from the requirements phase to the source code production. In this context, the UML is an interesting option for the embedded systems projects, leading to techniques to generate source code for both hardware and software. Currently, there are some works and commercial tools to generate source code from UML specifications to mainstream languages, such as C++ and Java. However, there are few works addressing the automatic source code generation for VHDL language, which is widely used in the embedded systems development. Thus, this work proposes a methodology to generate automatically VHDL source code from UML specifications. This methodology is supported by the GenERTiCA tool. A use case focused on the use of embedded systems for the maintenance systems is presented in this paper to demonstrate the feasibility of the proposed approach.