Title :
Improved Layout Dependence in High Performance SiGe Channel CMOSFETs
Author :
Liu, P.W. ; Chiang, W.T. ; Huang, Y.T. ; Tsai, T.L. ; Tsai, C.H. ; Tsai, C.T. ; Ma, G.H.
Author_Institution :
United Microelectron. Corp. (UMC), Tainan
Abstract :
The device degradation problem due to compressive STI in devices with narrow width or small diffusion length can be greatly relieved in SiGe channel devices with the post-STI epitaxy process. The (110)SiGe PMOS realizes 77% current gain over (100)Si PMOS at 1um gate width, and current gain is increased to 112% at 0.12um gate width. A 42% current improvement in (100)SiGe NMOS at 0.12um gate width is also reported. Moreover, for diffusion length ranging from 2.71um to 0.26um, less than 4% current variation is obtained in SiGe channel devices compared to the 8~12% current variation in Si channel devices. The improved layout dependence is resulted from the lower STI stress in post-STI SiGe epitaxy process.
Keywords :
Ge-Si alloys; MOSFET; epitaxial growth; CMOSFET; SiGe; layout dependence; post-STI epitaxy process; size 0.12 mum; size 1 mum; CMOSFETs; Compressive stress; Degradation; Epitaxial growth; Germanium silicon alloys; MOS devices; Microelectronics; Nanoscale devices; Piezoresistance; Silicon germanium;
Conference_Titel :
VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-1614-1
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2008.4530847