TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip

Author

Eghbal, Ashkan ; Yaghini, Pooria M. ; Yazdi, Siavash S. ; Bagherzadeh, Nader

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, Irvine, CA, USA

fYear

2014

fDate

1-3 Oct. 2014

Firstpage

92

Lastpage

97

Abstract

A reliable Three Dimensional Network-on-Chip (3D NoC) is required for future many-core systems. Through-silicon Via (TSV) is the prominent component of 3D NoC to support better performance and lower power consumption. Inductive TSV coupling has large disruptive effects on Signal Integrity (SI) and transmission delay. In this paper, TSV inductive coupling is analyzed based on technology process, TSV length, and TSV radius for a range of frequencies. A classification of inductive coupling voltage is presented for different TSV configurations. A novel coding technique is devised to mitigate the inductive coupling effects by adjusting the current flow pattern. Simulations for a 4×8 TSV matrix show 23% coupled voltage mitigation, imposing 12.5% information redundancy.

Keywords

network-on-chip; three-dimensional integrated circuits; 3D NoC; 3D network-on-chip; TSV length; TSV matrix; TSV radius; TSV-to-TSV inductive coupling; current flow pattern; inductive coupling voltage; lower power consumption; signal integrity; through-silicon via; transmission delay; voltage mitigation; Couplings; Encoding; Fault tolerance; Fault tolerant systems; Receivers; Three-dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on

Conference_Location

Amsterdam

Print_ISBN

978-1-4799-6154-2

Type

conf

DOI

10.1109/DFT.2014.6962067

Filename

6962067