Contribution to 3D SOI integration technologies using seeded laser ZMR and polycide refractory metallisation

Summary form only given. The integration of 3-D structures with one-level SOI over bulk is reported. Two kinds of structures have been studied: smart power circuits with bulk LDMOS and laterally displaced CMOS on SOI, and the so-called SMOS (stacked MOS) devices with n or pMOS bulk transistors and the complementary one stacked above using the recrystallized SOI layer. The seeded-zone-melting Ar⁺ laser recrystallization technique was used, and tantalum polycide structures provided a refractory interconnection over bulk devices. The CMOS-on-SOI developed was 3-D compatible, i.e no thermal steps were above 950°C and most were in the 800-900°C. The impact of such processes during the recrystallization step on the characteristics of n and pMOS bulk devices was studied. The leakage current of n-type devices was sometimes degraded. The influence of such parameters as isolation oxide thickness, recrystallization conditions, and CMOS process temperature range was also investigated