Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs

Author

Tambara, Lucas A. ; Lima Kastensmidt, Fernanda ; Rech, P. ; Frost, Christopher

Author_Institution

Inst. de Inf., UFRGS, Porto Alegre, Brazil

fYear

2014

fDate

1-3 Oct. 2014

Firstpage

153

Lastpage

158

Abstract

This paper explores the concept of Design Diversity Redundancy applied to SRAM-based FPGAs as a proposal to decrease failure rate. A 32-bit RISC processor MIPS was protected by coarse grain Triple Modular Redundancy (TMR) and by Diverse TMR (DTMR). Experimental results under neutron flux radiation show that DTMR can reduce in 40% the Failure in Time (FIT) of a system when compared to the standard MIPS while the coarse gain TMR could reduce the FIT in only 10%.

Keywords

SRAM chips; failure analysis; field programmable gate arrays; integrated circuit design; integrated circuit reliability; logic design; reduced instruction set computing; redundancy; DTMR; FIT; RISC processor MIPS; SRAM-based FPGAs; coarse grain triple modular redundancy; design diversity redundancy; diverse triple modular redundancy; failure in time; failure rate; neutron flux radiation; word length 32 bit; Discrete Fourier transforms; Fault tolerance; Fault tolerant systems; Nanotechnology; Very large scale integration; Design Diversity Redundancy; Fault Tolerance; SRAM-based FPGAs; Single Event Effects; Triple Modular Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on

Conference_Location

Amsterdam

Print_ISBN

978-1-4799-6154-2

Type

conf

DOI

10.1109/DFT.2014.6962070

Filename

6962070