Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors

Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches´ dominant share in die area and transistor budget, protecting them against soft errors is of paramount importance. Recent research has focused on the characterization and optimization for the reliability of data caches in single-core processors. As the mainstream processors enter the multi-/many-core era, the area share of the on-chip caches keeps increasing, which makes them more vulnerable to soft errors. However, few research work has studied the vulnerability of the on-chip caches in the context of the cache coherence protocols. In this work, we propose to characterize the soft error vulnerability of the L1 data cache in chip-multiprocessors (CMPs) under the influence of different cache coherence protocols. This study aims to provide insights into cache vulnerability behaviors in CMPs as well as guidance in designing reliable cache coherence protocols. Furthermore, an early-invalidation scheme is proposed to reduce the overall vulnerability factor of the data caches in CMPs. Benchmarking is carried out to showcase the effectiveness of our approach.