A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

This paper presents a low-power 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input with a novel Built-in Self Calibration (BiSC) feature to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as fore-ground operation so that low power consumption is achieved. Consequently, the mismatch error of the DAC can be minimized and the SAR based ADC operates without any extra power dissipation for the circuitry of self calibration during normal operation. The prototype was designed using 0.13μm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.2 dB and consumes 3.57 mW with 1.2V supply voltage and sampling rate of 32 MS/s. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 45% and 51%, respectively.