An instance-based SER analysis in the presence of PVTA variations

As semiconductor technology has entered into the nanoscale regime, Single Event Transient (SET) became one of the major challenging issues for silicon chips. Susceptibility to soft error is even becoming more severe in the presence of Process, Voltage, Temperature, and transistor Aging (PVTA) variations. In this paper, we model and analyze the impacts of PVTA on the susceptibility of VLSI chips to SET. We show that higher PVTA results in significant reduction of critical charge (i.e, higher glitch generation) of silicons while electrical masking (preventing glitch propagation) is improved. In addition, we propose a holistic instance-based systematic methodology to calculate the Soft Error Rate (SER) of combinationals considering PVTA variations. The simulation results for various ITC´99 benchmark circuits show that disregarding PVTA information results in 76% error in the estimated SER on average. Moreover, according to the results, SER increases by 70% on average in the first years of circuit lifetime due to transistor aging and then it is almost saturated.