DocumentCode
159501
Title
Shortest path reduction in a class of uniform fault tolerant networks
Author
Joshi, Prashant D. ; Hamdioui, Said
fYear
2014
fDate
1-3 Oct. 2014
Firstpage
234
Lastpage
239
Abstract
Shortest path determination in a class of optimally fault tolerant networks designed using modified line graphs is described here. Appropriate node naming allows the shortest paths to be determined in 0(log n) steps. This is applicable even in the presence of node failures, without loops or backtracking. The stretch of the network is maintained at the theoretically minimum value possible of one.
Keywords
backtracking; fault tolerance; graph theory; backtracking; fault tolerant networks; line graphs; node naming; path reduction; Discrete Fourier transforms; Fault tolerance; Fault tolerant systems; Nanotechnology; Very large scale integration; Connectivity; Diameter of graph; Fault Tolerance; Line Graphs; Node naming; Shortest Path in Networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on
Conference_Location
Amsterdam
Print_ISBN
978-1-4799-6154-2
Type
conf
DOI
10.1109/DFT.2014.6962102
Filename
6962102
Link To Document