DocumentCode
159505
Title
A runtime manager for gracefully degrading SoCs
Author
Tzilis, Stavros ; Sourdis, Ioannis
Author_Institution
Comput. Sci. & Eng. Dept., Chalmers Univ. of Technol., Gothenburg, Sweden
fYear
2014
fDate
1-3 Oct. 2014
Firstpage
216
Lastpage
221
Abstract
The increasing number of transistors integrated on a single chip comes with the blessing of raw computational power and the curse of susceptibility to various kinds of faults. On top of increased defect densities, wearout effects mean that the testing verdict at fabrication time cannot be trusted throughout the chip lifetime. However, extra computational power presents the opportunity to build gracefully degrading MPSoCs. Re-configurable components and flexible workloads, along with runtime support, enable MPSoCs to deal with permanent faults degrading one or more system aspects, such as performance, energy efficiency and delivered functionality, instead of failing. In this manner, chip life is prolonged and safety is increased. In this work Graceful Degradation (GD) is formulated as an optimization problem in the context of MPSoCs. As such, its possible solutions can be evaluated in a parameterizable and consistent manner. An attempt at a runtime solution for a heterogeneous 4-core SoC is made and the resulting GD manager is evaluated in terms of speed and accuracy, with a use case combining essential automotive tasks and non-essential additional features. On average, it is found to produce a solution 89% as good as the optimal, in 4.3μsec running on one core of a common modern CPU.
Keywords
circuit optimisation; multiprocessing systems; system-on-chip; CPU; GD manager; automotive tasks; chip lifetime; defect densities; graceful degradation; gracefully degrading MPSoCs; heterogeneous 4-core SoC; optimization problem; permanent faults; reconfigurable components; runtime manager; time 4.3 mus; Automotive engineering; Availability; Degradation; Hardware; Quality of service; Reduced instruction set computing; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on
Conference_Location
Amsterdam
Print_ISBN
978-1-4799-6154-2
Type
conf
DOI
10.1109/DFT.2014.6962106
Filename
6962106
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