A Hybrid Genetic Algorithm with Critical Primary Inputs Sharing and Minor Primary Inputs Bits Climbing for Circuit Maximum Power Estimation

With continuously shrinking of ICs device feature sizes, input pattern dependent maximum power in a clock cycle (CMP) for digital circuit has become a challenging issue in power network verification and optimization. In this paper, a novel hybrid genetic algorithm (HGA) that takes advantages of critical primary inputs sharing and minor primary inputs bits climbing is proposed for CMP estimation. Critical and minor primary inputs are defined based on their possible contribution to CMP, which is defined as the fitness value for the input vector pair. Compared with simple genetic algorithm, our method achieves up to 25.7% improvement on CMP estimation for ISCAS85 benchmark circuits with a faster convergence speed and less than 6% computation overhead in average.