High performance CMOS in silicide to sapphire (CMOS/STS)

Summary form only given, as follows. HIgh-performance circuitry has been designed, simulated, fabricated, and tested in 100-nm thick double-solid-phase-epitaxy SOS. The source and drain regions outside the oxide sidewall spacers were silicided to the sapphire substrate, thereby providing self-aligned contacts to the transistors as well as an additional level of interconnects. The n⁺ and p⁺ regions under the oxide sidewalls serve as the actual source and drain regions. Ring oscillators with a 1.25-μm gate length exhibit 120-ps gate delays, which compare well to simulation results of 125 ps. Simulations of electron-beam-written 0.5-μm-gate-length ring oscillators predict gate delays of about 40 ps