Title :
Architecture and design methodology of the RBF-DDA neural network
Author :
Aberbour, Mourad ; Mehrez, Habib
Author_Institution :
ASIM Lab., Univ. Pierre et Marie Curie, Paris, France
Abstract :
This paper presents a novel implementation of the RBF-DDA (Radial Basis Functions-Dynamic Decay Adjustment) neural network. We investigate the architectural design and the hardware implementation. The features of this design are the possibility of mapping the architecture on different standard cells libraries as well as FPGA´s, and mainly its modularization. This is an example which reflects the new trend in design methodologies relying on re-use and IP blocks. Indeed, the architecture is implemented using intensively the module generator and macro-blocks concept. The design is thus readily reusable, flexible and upgradable. The architecture is parameterized in terms of the precision of the data processed by the network and in terms of the size of the network itself (number of neurons). The neural network is used in the classification of the image signatures which are extracted from gray-level images using the Gabor-Morlet wavelets and some data compression schemes. The RBF-DDA approach implements the Probabilistic Neural Network model. The activation function is a Gaussian which models the probability distribution of the categories to be differentiated. In the introduction we briefly describe the whole recognition system and we scan rapidly the hardware implementation experiences. The second section discusses the RBF-DDA algorithm and architecture. Then we present the architecture and the VLSI design methodology of the RBF network. Finally, we present some implementation results
Keywords :
Gaussian distribution; VLSI; circuit CAD; image classification; image processing equipment; integrated circuit design; learning (artificial intelligence); neural chips; neural net architecture; parallel architectures; FPGAs; Gabor-Morlet wavelets; RBF-DDA neural network; VLSI design; activation function; architectural design; data compression schemes; design methodology; dynamic decay adjustment; gray-level images; hardware implementation; image signature classification; macro-blocks; modularization; module generator; probabilistic neural network model; probability distribution; radial basis functions; recognition system; standard cells libraries; Data compression; Data mining; Design methodology; Field programmable gate arrays; Hardware; Libraries; Neural networks; Neurons; Probability distribution; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.703974