• DocumentCode
    159701
  • Title

    Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis

  • Author

    Fort, Blair ; Canis, Andrew ; Choi, Jang-Young ; Calagar, Nazanin ; Ruolong Lian ; Hadjis, Stefan ; Yu Ting Chen ; Hall, Mathew ; Syrowik, Bain ; Czajkowski, Tomasz ; Brown, Shannon ; Anderson, Jon

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
  • fYear
    2014
  • fDate
    26-28 Aug. 2014
  • Firstpage
    120
  • Lastpage
    129
  • Abstract
    LegUp [1] is an open-source high-level synthesis (HLS) tool that accepts a C program as input and automatically synthesizes it into a hybrid system. The hybrid system comprises an embedded processor and custom accelerators that realize user-designated compute-intensive parts of the program with improved throughput and energy efficiency. In this paper, we overview the LegUp framework and describe several recent developments: 1) support for an embedded ARM processor, as is available on Altera´s recently released SoC FPGA, 2) HLS support for software parallelization schemes -- pthreads and OpenMP, 3) enhancements to LegUp´s core HLS algorithms that raise the quality of the auto-generated hardware, and, 4) a preliminary debugging and verification framework providing C source-level debugging of HLS hardware. Since its first release in 2011, LegUp has been downloaded over 1000 times by groups around the world, providing a powerful platform for new research in high-level synthesis algorithms and embedded systems design.
  • Keywords
    C language; computer debugging; embedded systems; field programmable gate arrays; high level synthesis; microcontrollers; parallel processing; public domain software; system-on-chip; C program; C source-level debugging; HLS algorithms; HLS hardware; HLS tool; LegUp; OpenMP; SoC FPGA; embedded ARM processor; high-level synthesis tool; hybrid system; open-source; processor-accelerator embedded systems; software parallelization schemes; user-designated compute-intensive parts; Benchmark testing; Field programmable gate arrays; Hardware; Optimal scheduling; Pipeline processing; Software; FPGAs; High-level synthesis; accelerators; embedded systems; performance; scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Embedded and Ubiquitous Computing (EUC), 2014 12th IEEE International Conference on
  • Conference_Location
    Milano
  • Type

    conf

  • DOI
    10.1109/EUC.2014.26
  • Filename
    6962276