Simulating systolic arrays on MasPar machines

Systolic arrays and SIMD computers apparently share several common features. By careful analysis we show that current SIMD computers are in no way able to match the performance of general systolic arrays, due to small bandwidth and inflexible communication between host computer and SIMD processor array, as well as insufficient local memory on the processor elements. Quantitative experimental research on MasPar MP-I and MP-2 SIMD machines validates our theoretical conclusions. Our research implicitly exhibits why SIMD computers frequently do not match the expectations. We propose modifications of current SIMD architectures that could considerably improve the performance of SIMD machines.