Design and operating characteristics of voltage comparator using MTCMOS circuits

This paper describes low power and high performance comparator with hysteresis effect at 45 nm technology. Simulation of Comparator with hysteresis as compared same configuration without hysteresis provides leakage power 4.867 µW. Comparator is to be designed propose to perform comparison of voltage at two terminals with reference voltage 500 mV, since the input are balanced. Leakage power performance optimization of comparator using Multi-threshold (MCTMOS) logic. Leakage power is achieved to optimal value of 73.03 femto watt. Delay is reduced to 12% with hysteresis in comparison to without hysteresis. Voltage gain is higher up to 40% as compared with comparator (without hysteresis). Offset value is reduced to 80% with hysteresis effect. Inverter output buffer stage followed the decision stage is reduces the offset error.