Title :
Estimation of short-circuit power dissipation and its influence on propagation delay for static CMOS gates
Author :
Hirata, Akio ; Onodera, Hidetoshi ; Tamaru, Keikichi
Author_Institution :
Dept. of Electron. & Commun., Kyoto Univ., Japan
Abstract :
We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering current flowing from the input node to the output node through gate capacitances, the accuracy is improved significantly. The error of our formula for a CMOS inverter is less than 15% from circuit simulation in most cases. We also derive delay formulae considering the short-circuit current and the current flowing through gate capacitance. The error of this formula is smaller than 13% in our experiments. Since these formulae calculate the short-circuit power dissipation and the delay accurately and quickly, they can be applied to power sensible CAD tools
Keywords :
CMOS logic circuits; circuit analysis computing; delays; logic gates; piecewise-linear techniques; short-circuit currents; CMOS inverter; circuit simulation; gate capacitances; piece-wise linear function; power sensible CAD tools; propagation delay; short-circuit current; short-circuit power dissipation; static CMOS logic gates; CMOS logic circuits; Capacitance; Delay estimation; Inverters; Logic design; Logic gates; MOSFETs; Power dissipation; Propagation delay; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.542133
