Title :
A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC)
Author :
Joyner, James W. ; Zarkesh-Ha, Payman ; Meindl, James D.
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
A global net-length distribution for three-dimensional system-on-a-chip architectures is derived to quantify the impact of the number of strata, or active layers, on the length of the long global interconnects. Model projections indicate a reduction in the global net length as the square root of the number of strata, thus enabling a significant reduction in chip footprint area, power dissipation, and global cycle time in comparison to a two-dimensional system-on-a-chip. Unlike its homogeneous counterpart, the vertical integration of a heterogeneous system is not limited by the density of interstratal interconnects. The size of the large megacells, especially memory, may restrict the effectiveness of a large number of strata
Keywords :
integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; stochastic processes; active layers; chip footprint area; effectiveness; global cycle time; global interconnects; global net length; global net-length distribution; interstratal interconnects; megacells; number of strata; power dissipation; stochastic distribution; three-dimensional system-on-a-chip architectures; vertical integration; Clocks; Demand forecasting; Integrated circuit interconnections; Joining processes; Power dissipation; Power system interconnection; Power system modeling; Stochastic systems; System-on-a-chip; Wiring;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954688
