DocumentCode
1598494
Title
Cell designs for self-timed FPGAs
Author
Traver, Cherrice ; Reese, Robert B. ; Thornton, Mitch A.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
175
Lastpage
179
Abstract
A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timed circuits that are insensitive to delays between gates. The target implementation is a self-timed FPGA architecture composed of PL gates. A PL gate design based on a 4-input lookup table is presented. Power and performance estimates of two designs are given and are compared to their clocked counterparts
Keywords
asynchronous circuits; field programmable gate arrays; integrated circuit design; logic design; table lookup; 4-input lookup table; asynchronous design; cell designs; phased logic gates; phased logic systems; self-timed FPGA architecture; self-timed circuits; self-timed programmable architecture; Circuits; Clocks; Delay; Design methodology; Encoding; Field programmable gate arrays; Logic design; Logic gates; Table lookup; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location
Arlington, VA
Print_ISBN
0-7803-6741-3
Type
conf
DOI
10.1109/ASIC.2001.954693
Filename
954693
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