Design verification techniques for system level testing using ASIC level BIST implementations

Author

Stroud, Charles E. ; Liang, Gang

Author_Institution

Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA

fYear

1993

Firstpage

140

Lastpage

143

Abstract

Requirements and design verification techniques for system level testing using BIST implementations in ASICs are discussed. A logic simulation technique is presented which determines whether reproducable BIST results can be obtained during system level testing. Using this approach, problems which could lead to nonreproducible BIST results during system level testing can be easily identified and corrected during device level of design,

Keywords

application specific integrated circuits; asynchronous circuits; automatic test software; built-in self test; circuit CAD; fault diagnosis; integrated circuit design; integrated circuit testing; logic CAD; logic testing; ASICs; ATPG; BIST implementations; asynchronous circuits; design verification; logic simulation technique; reproducable BIST; system level testing; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Logic devices; Logic testing; Packaging; Software testing; System software; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410826

Filename

410826

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1598607