Title :
Self-aligned gate JFET modeling and characterisation
Author :
Amon, S. ; Vrtacnik, D. ; Resnik, D. ; Krizaj, D.
Author_Institution :
Fac. of Electr. Eng., Ljubljana Univ., Slovenia
fDate :
6/21/1905 12:00:00 AM
Abstract :
An approach with a self-aligned gate JFET, enabling device isolation and integration with standard planar discrete device technology, is studied. Process modeling together with 2D device modeling provide adequate information for test structure design and fabrication. Measured results on fabricated test structures prove correct device operation and are in reasonable agreement with predictions from modeling
Keywords :
junction gate field effect transistors; semiconductor device breakdown; semiconductor device measurement; semiconductor device models; 2D device modeling; JFET characterisation; JFET modeling; device isolation; self-aligned gate JFET; standard planar discrete device technology; Doping profiles; Epitaxial growth; Fabrication; Intelligent sensors; Isolation technology; Medical simulation; Microelectromechanical systems; Predictive models; Semiconductor process modeling; Testing;
Conference_Titel :
Africon, 1999 IEEE
Conference_Location :
Cape Town
Print_ISBN :
0-7803-5546-6
DOI :
10.1109/AFRCON.1999.821943
