DocumentCode
1598967
Title
Self-aligned gate JFET modeling and characterisation
Author
Amon, S. ; Vrtacnik, D. ; Resnik, D. ; Krizaj, D.
Author_Institution
Fac. of Electr. Eng., Ljubljana Univ., Slovenia
Volume
2
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
1163
Abstract
An approach with a self-aligned gate JFET, enabling device isolation and integration with standard planar discrete device technology, is studied. Process modeling together with 2D device modeling provide adequate information for test structure design and fabrication. Measured results on fabricated test structures prove correct device operation and are in reasonable agreement with predictions from modeling
Keywords
junction gate field effect transistors; semiconductor device breakdown; semiconductor device measurement; semiconductor device models; 2D device modeling; JFET characterisation; JFET modeling; device isolation; self-aligned gate JFET; standard planar discrete device technology; Doping profiles; Epitaxial growth; Fabrication; Intelligent sensors; Isolation technology; Medical simulation; Microelectromechanical systems; Predictive models; Semiconductor process modeling; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Africon, 1999 IEEE
Conference_Location
Cape Town
Print_ISBN
0-7803-5546-6
Type
conf
DOI
10.1109/AFRCON.1999.821943
Filename
821943
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