DocumentCode
1599004
Title
A four-transistor CMOS SRAM cell
Author
Joubert, T.-H. ; Seevinck, E. ; du Plessis, M.
Author_Institution
Dept. of Electr. & Electron. Eng., Pretoria Univ., South Africa
Volume
2
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
1173
Abstract
In CMOS, an SRAM cell containing six transistors is generally used. If a smaller number of transistors and fewer connection lines were possible, the packing density of SRAM chips may be improved. A reduce-area four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed in this paper
Keywords
CMOS memory circuits; SRAM chips; integrated circuit layout; SRAM chips; four-transistor CMOS SRAM cell; packing density improvement; reduce-area SRAM cell; standard digital CMOS process; CMOS logic circuits; CMOS process; CMOS technology; Inverters; MOSFETs; Monitoring; Random access memory; SRAM chips; Thin film transistors; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Africon, 1999 IEEE
Conference_Location
Cape Town
Print_ISBN
0-7803-5546-6
Type
conf
DOI
10.1109/AFRCON.1999.821945
Filename
821945
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