DocumentCode
1599090
Title
A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop
Author
Yang, Sung-Hyun ; Lee, Cheol-Nee ; Cho, Kyoung-Rok
Author_Institution
Dept. of Comput. & Commun. Eng., Chung-Buk Nat. Univ., Cheongju, South Korea
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
276
Lastpage
280
Abstract
A dual-modulus divide-by-128/129 prescaler has been designed using 0.6-μm CMOS technology. A new charge sharing free dynamic D-flip-flop for high-speed operation and low-power consumption is examined in the circuits. The simulated maximum operating frequency and the current consumption of the prescaler are 1.97-GHz and 7.453 mA at 5-V supply voltage, respectively
Keywords
CMOS logic circuits; flip-flops; high-speed integrated circuits; low-power electronics; prescalers; 0.6 micron; 1.97 GHz; 5 V; 7.453 mA; CMOS dual-modulus prescaler; charge sharing free dynamic D-flip-flop; current consumption; high-speed operation; low-power circuit; maximum operating frequency; CMOS technology; Circuit simulation; Clocks; Energy consumption; Flip-flops; Frequency; Logic; Phase locked loops; Synthesizers; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location
Arlington, VA
Print_ISBN
0-7803-6741-3
Type
conf
DOI
10.1109/ASIC.2001.954711
Filename
954711
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