Optimum sigma-delta (Σ-Δ) de-modulator filter implementation via FPGA

Sigma-delta (Σ-Δ) modulators have been widely used over the last few decades, in various signal processing applications. Usually, sigma-delta modulators produce single-bit outputs and thus are well suited for VLSI circuits which could be implemented using a small number of multipliers. For improved signal-to-noise (quantization) performances, higher order modulator schemes with multiloop and multi-stage architecture are utilized in most of the sigma-delta applications. The quantization noise behaviour of these higher order modulators is well known. Based on the quantization noise characteristics various de-modulator filter architectures, such as optimal FIR, Sinc filters and Laguerre HR filters are reported in the literature. In this paper, the VLSI implementation issues of these various demodulator filters are investigated. For this purpose the demodulators are implemented using Field Programmable Gate Array (FPGA) architecture