Title :
Synchronization with multiprocessor caches
Author :
Lee, Joonwon ; Ramachandran, U.
Author_Institution :
Sch. of Inf. & Comput. Sci., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
A new lock-based cache scheme which incorporates synchronization into the cache coherency mechanism is presented. With this scheme high-level synchronization primitives, as well as low-level ones, can be implemented without excessive overhead. Cost functions for well-known synchronization methods are derived for invalidation schemes, write update schemes, and the authors´ lock-based scheme. To predict the performance implications of the new scheme accurately, a new simulation model embodying a widely accepted paradigm of parallel programming is developed. It is shown that that authors´ lock-based protocol outperforms existing cache protocols
Keywords :
buffer storage; concurrency control; performance evaluation; synchronisation; cache coherency mechanism; cache protocols; cost functions; high-level synchronization primitives; invalidation schemes; lock-based cache scheme; overhead; parallel programming; performance implications; simulation model; synchronization; write update; Access protocols; Broadcasting; Computer science; Costs; Hardware; Parallel programming; Predictive models; Programming profession; Random access memory; Traffic control;
Conference_Titel :
Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-8186-2047-1
DOI :
10.1109/ISCA.1990.134504