Title :
Circuit partitioning for pseudo-exhaustive test
Author :
Chen, Chien-In Henry
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
Pseudo-exhaustive testing is not suitable to total dependency circuits in which at least one output is functionally dependent on all the inputs. Even for a partial dependency circuit, the size of a pseudo-exhaustive test set may still be too large to be applicable in practice. In such cases, pseudo-exhaustive test can be achieved by partitioning techniques. The principle is to partition the circuit into subcircuits such that the output of each subcircuit is functionally dependent on only a small number of inputs. Then the subcircuits are pseudo-exhaustively tested. Moreover, since the time complexity of test generation and fault simulation grows faster than a linear function of circuit size, it is cost-effective to partition large circuits to reduce these costs. A circuit partitioning tool, Autonomous, is presented to partition digital combinational portions of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. The effectiveness of partitioning method is shown by applying the method to different examples and practical VLSI designs
Keywords :
VLSI; application specific integrated circuits; automatic test software; combinational circuits; integrated circuit testing; logic CAD; logic partitioning; logic testing; ATPG; Autonomous; VLSI; circuit partitioning; circuit partitioning tool; digital combinational portions; pseudo-exhaustive test; structural subcircuits; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Contracts; Cost function; Ducts; Iterative algorithms; Partitioning algorithms; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410828