The Design of High Performance Barrel Integer Adder

This paper proposes a new kind of parallel integer addition algorithm - the barrel integer addition algorithm on the basis of researching the structure of half adder. It also elaborates the principle and structure of barrel integer addition algorithm, analyses the time and the degree of complexity in the area of the algorithm and at the same time compares it with the traditional integer addition algorithm. We realized that the 16-bit barrel integer adder using Verilog HDL and verifies comprehensively in the Altera device. The result shows that the speed of the barrel integer adder designed in this paper improves obviously on the basis of a small increase of area, which lays the foundation for the improvement of the multiplier performance.