Title :
Analysis of die-to-die vertical crosstalk between Clock-tree and Voltage Controlled Oscillator in 3-D IC
Author :
Sangrok Lee ; Kyoungchoul Koo ; Joungho Kim
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Abstract :
Vertical crosstalk problem between digital and analog circuit components in 3-D IC can severely degrade the 3-D IC system performance. In this paper, we analyze the performance degradation mechanism of 3-D IC that induced by vertical crosstalk between Clock-tree and Voltage Controlled Oscillator (VCO). The 3-D IC test chip which contains Clock-tree and spiral inductor of VCO is fabricated. Lumped component vertical crosstalk model is proposed and it is validated with measurement result. Using validated vertical crosstalk model and spice circuit of VCO, circuit level simulation is performed. Performance degradation mechanism of VCO in 3-D IC is analyzed by separation of noise coupling path approach, and the main mechanism is revealed as high frequency multiplicative noise on signal path.
Keywords :
crosstalk; integrated circuit noise; three-dimensional integrated circuits; voltage-controlled oscillators; 3D IC test chip; 3D integrated circuits; SPICE circuit; circuit level simulation; clock-tree; die-to-die vertical crosstalk; high frequency multiplicative noise; noise coupling path; performance degradation mechanism; spiral inductor; voltage controlled oscillator; Clocks; Crosstalk; Inductors; Integrated circuits; Noise; Spirals; Voltage-controlled oscillators; 3-D IC; Clock-tree; Crosstalk; DDR3 DRAM; Lumped component model; S-parameter; Spiral Inductor; Through Silicon Via (TSV); Voltage Controlled Oscillator(VCO); Voltage transfer ratio; Wire bonding;
Conference_Titel :
Electromagnetic Compatibility (EMC), 2011 IEEE International Symposium on
Conference_Location :
Long Beach, CA, USA
Print_ISBN :
978-1-4577-0812-1
DOI :
10.1109/ISEMC.2011.6038279
