A VLSI design of a high-speed Reed-Solomon decoder

Author

Lee, Hanho

Author_Institution

Platform IP Lab., Agere Syst., Allentown, PA, USA

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

316

Lastpage

320

Abstract

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurred in the transmission process. This paper presents a VLSI implementation of a high-speed 8-error correcting, RS(255,239) decoder architecture using a modified Euclidean algorithm for communication systems. The RS decoder has been designed and implemented with a 0.16-μm CMOS standard cell technology with a supply voltage of 1.5 V. The results show that the proposed RS decoder operates at a clock frequency of 670 MHz and has a data processing rate of 5.36 Gbit/s

Keywords

CMOS digital integrated circuits; Reed-Solomon codes; VLSI; decoding; digital signal processing chips; error correction codes; high-speed integrated circuits; integrated circuit design; pipeline processing; 0.16 micron; 1.5 V; 5.36 Gbit/s; 670 MHz; 8-error correcting decoder architecture; CMOS standard cell technology; Reed-Solomon decoder; VLSI design; VLSI implementation; communication systems; high-speed RS decoder architecture; modified Euclidean algorithm; CMOS process; CMOS technology; Clocks; Data processing; Decoding; Frequency; Protection; Reed-Solomon codes; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6741-3

Type

conf

DOI

10.1109/ASIC.2001.954719

Filename

954719