Title :
Circuit challenges and proposed solutions targeting nanometer technologies
Author :
Secareanu, Radu M. ; Jones, Marquis ; Sadd, M. ; White, Bruce ; Maniar, Papu
Author_Institution :
Semicond. Products Sector, Motorola Inc., Mesa, AZ, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
Presently, R&D organizations of leading semiconductor companies are focusing their efforts on developing devices, technologies, and applications for below the 100 nanometer feature size. Specific device, circuit, and system challenges for the 30 nanometer feature size in present R&D focus at Motorola, are analyzed in this paper. Circuit solutions that will ease the device and technology development while allowing the stringent device, circuit, and system performance requirements for the 30 nanometer node to be met, are proposed
Keywords :
CMOS integrated circuits; integrated circuit technology; nanotechnology; research initiatives; silicon-on-insulator; Motorola; R&D organizations; Si; bulk CMOS; circuit performance requirements; device development; device performance requirements; double-gate SOI devices; nanometer technology; power dissipation; reliability issues; semiconductor companies; technology development; CMOS logic circuits; Circuit noise; Clocks; Crosstalk; Electromagnetic interference; Nanoscale devices; Noise level; Research and development; Semiconductor device noise; System-on-a-chip;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954721
