Development of underfilling and thermo-compression bonding processes for stacking multi-layer 3D ICs

Assembling multi-layer thinned Si chips to form 3D ICs in a fast, reliable, and cost-effective manner is one of the key processes to enable wider application and commercialization of 3D integration. In this paper the essential aspects of process development for stacking multi-layer 3D ICs are investigated. Combining thermo-compression bonding (TCB) process and the usage of pre-applied wafer-level underfill (WLUF) can significantly reduce the process complexity and time. A novel vertical collective bonding method is proposed and experimentally implemented, showing great potential in process improvement and throughput increase. Based on these techniques, stacking of multiple layers of 50 μm thick chips on bottom dies is successfully demonstrated. Daisy chains consisted of TSVs 5 μm in diameter and 20 μm pitch micro joints, in both bump-to-bump (Sn-to-Cu) and TSV-to-bump (Cu-to-Cu) bonding schemes, are connected with good electrical yield between all the stacked layers.