A true block pipelined programmable Reed-Solomon CODEC for high-speed/low-power applications

Author

Kwon, Hyung-Joon ; Lee, Jaeshin ; Lee, Seunghoon ; Jeong, BongYoung

Author_Institution

Samsung Electron., Kyunggi-Do, South Korea

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

352

Lastpage

355

Abstract

Proposes a Reed-Solomon CODEC architecture. The chip was fabricated using 0.35μm technology. Since it was implemented as a programmable CODEC which,can correct up to 16 errors/32 erasures at once, it has versatility regardless of the number of correctable errors and the length of codeword for various applications. Suggested RS-CODEC has "true block pipelined architecture" in which frame latency is equal to the length of codeword leading to maximize throughput to achieve high-speed and low-power at the same time. The input data rate can amount to 100MByte per sec

Keywords

Reed-Solomon codes; codecs; error correction codes; high-speed integrated circuits; low-power electronics; pipeline processing; 0.35 micron; 100 MByte/s; block pipelined programmable Reed-Solomon CODEC; codeword length; correctable errors; high-speed applications; input data rate; low-power applications; throughput; Clocks; Codecs; Decoding; Delay; Error correction; Error correction codes; Pipeline processing; Polynomials; Reed-Solomon codes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6741-3

Type

conf

DOI

10.1109/ASIC.2001.954726

Filename

954726