A highly reliable pyramid tree network architecture

Author

Mohsin, M. ; Gupta, Bldyut

Author_Institution

Southern Illinois Univ., Carbondale, IL, USA

fYear

1990

Firstpage

363

Lastpage

372

Abstract

A highly fault-tolerant pyramid tree network architecture is designed and analyzed. The idea of modularity is used to ease the VLSI implementation of the architecture. It has been shown that, besides tolerating failures in the operational processing elements, the proposed design can tolerate the spare processing element failures and link failures as well. An optimal switch structure, a well-defined reconfiguration algorithm, and a VLSI layout of the proposed design are also presented. A reliability analysis is provided, and it shows a substantial increase in system reliability of the proposed fault-tolerant pyramid tree over its nonredundant counterpart

Keywords

VLSI; circuit layout CAD; fault tolerant computing; multiprocessor interconnection networks; reliability; trees (mathematics); VLSI; VLSI layout; fault-tolerant pyramid tree network architecture; optimal switch structure; reconfiguration algorithm; reliability analysis; system reliability; Algorithm design and analysis; Binary trees; Communication switching; Computer architecture; Computer network reliability; Computer science; Fault tolerance; Fault tolerant systems; Switches; Tree graphs;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Computing, 1990., Proceedings of the 1990 Symposium on

Conference_Location

Fayetteville, AR

Print_ISBN

0-8186-2031-5

Type

conf

DOI

10.1109/SOAC.1990.82197

Filename

82197