IP protection for VLSI designs via watermarking of routes

Author

Narayan, Naveen ; Newbould, Rexford D. ; Carothers, J.D. ; Rodriguez, Jefrey J. ; Holman, W.

Author_Institution

Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

406

Lastpage

410

Abstract

Intellectual property protection (IPP) has become a major concern in today´s CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each

Keywords

VLSI; analogue integrated circuits; application specific integrated circuits; circuit CAD; copy protection; industrial property; integrated circuit design; integrated circuit noise; logic CAD; mixed analogue-digital integrated circuits; network routing; ASIC/SOC industries; CAD; VLSI; analog design; bends; digital design; embedding; intellectual property protection; mixed-signal design; noise tolerance; physical design; vias; watermarking technique; Application specific integrated circuits; Design automation; Design methodology; Intellectual property; Protection; Robustness; Signal design; System-on-a-chip; Very large scale integration; Watermarking;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Conference_Location

Arlington, VA

Print_ISBN

0-7803-6741-3

Type

conf

DOI

10.1109/ASIC.2001.954736

Filename

954736