Title :
Flexible IP blocks for customized synthesis
Author :
Ziegler, Matthew M. ; Stan, Mircea R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
In order to leverage the optimality of custom design with the efficiencies of design synthesis and component reuse we present a new approach for IP blocks. A flexible architecture sized transistors block (FAST block) provides the means of locating an optimal architecture and transistor sizing scheme for the given synthesis constraints. In this paper we first introduce the FAST block methodology. We then present the foundation of a FAST block model for prefix adders. We follow with an example of the FAST block prefix adder model in action for various synthesis constraints
Keywords :
adders; application specific integrated circuits; circuit optimisation; industrial property; integrated circuit design; logic CAD; multiplying circuits; component reuse; custom design; design synthesis; flexible IP blocks; flexible architecture sized transistors block; prefix adders; synthesis constraints; transistor sizing scheme; Adders; Application specific integrated circuits; Constraint optimization; Design methodology; Design optimization; Integrated circuit synthesis; Productivity; Silicon; System-on-a-chip; Time to market;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954738
