A highly portable, self-stimulating and self-testing reliability test chip for ASIC products

Author

Erhart, David L. ; Colunga, Tomas ; Lopez, David

Author_Institution

Motorola, Inc., Chandler, AZ, USA

fYear

1993

Firstpage

160

Lastpage

163

Abstract

The use of a highly portable ASIC design, a reliability test chip (RTC), that has been successfully used for the reliability assessment of two generations of CMOS products is described. The RTC design has many features that make it an excellent vehicle for performing silicon process and package reliability qualifications. This design comprises a repetitive megacell-based core that is supported by a standardized vector generator and verification circuitry. The standardization of the design allows easy portability to various base array sizes and new silicon process technologies

Keywords

CMOS logic circuits; application specific integrated circuits; built-in self test; cellular arrays; integrated circuit design; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; logic testing; CMOS products; highly portable ASIC design; logic megacell; package reliability; repetitive megacell-based core; self-stimulating; self-testing reliability test chip; standardized vector generator; verification circuitry; Application specific integrated circuits; Automatic testing; Built-in self-test; Extrapolation; Life testing; Product design; Qualifications; Silicon; Stress; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410830

Filename

410830