Title :
Evaluating the impact of architectural-level optimizations on clock power
Author :
Duarte, David ; Narayanan, Vijaykrishnan ; Irwin, M.J. ; Kandemir, Mahmut
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
A clock energy model is incorporated into a cycle-accurate energy simulator for an embedded architecture, which also resembles processor cores present in System-on-a-Chip (SoC) designs. This framework is used to study and quantify the influence on clock energy of several architectural-level decisions and their relative impact on the overall system energy. The design cases include various cache architectures and support for clock gating at different levels (global and local). At the software level, the influence on clock energy of power-oriented memory compiler optimizations is assessed
Keywords :
VLSI; cache storage; circuit optimisation; clocks; energy conservation; integrated circuit design; integrated circuit modelling; integrated memory circuits; logic CAD; power consumption; System-on-a-Chip design; architectural-level decisions; cache architectures; clock energy model; clock gating; cycle-accurate energy simulator; embedded architecture; power-oriented memory compiler optimisation; software level; Circuit simulation; Clocks; Computer architecture; Computer science; Energy consumption; Network topology; Optimizing compilers; Phase locked loops; Power system modeling; System-on-a-chip;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954743
