Title :
A low-power variable resolution analog-to-digital converter
Author :
Aust, Carrie ; Sam ha, Dong
Author_Institution :
Microelectron. Div., IBM Corp., Research Triangle Park, NC, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
A method to reduce the power dissipation of analog-to-digital converters (ADCs) in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this paper, we present an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is, a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Our ADC is implemented in a 0.35 μm CMOS-technology with a-single-ended 3.3 V power supply. This ADC implementation has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average, of 10 percent less power when the resolution-is decreased by two bits
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); cyclic codes; digital radio; power consumption; radio access networks; switched current circuits; 0.35 μm CMOS; 0.35 micron; 12 bit resolution; 3.3 V; 3.3 V power supply; 6.35 mW; ADC; analog-to-digital converters; power dissipation; power dissipation 6.35 mW; redundant signed-digit implementation; resolution; switched current circuit; wireless digital communication; Analog-digital conversion; CMOS technology; Iterative algorithms; Microelectronics; Power dissipation; Power supplies; Switching converters; Telecommunication computing; Very large scale integration; Wireless communication;
Conference_Titel :
ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International
Conference_Location :
Arlington, VA
Print_ISBN :
0-7803-6741-3
DOI :
10.1109/ASIC.2001.954745
