Optimized FPGA-based implementation of down-sampling filter for wide band radio receiver

To increase both the integration and adaptability to multiple RF communication standards, channel selection need to be performed on chip at base-band. This paper presents a low-power design and an area-efficient FPGA implementation of digital filtering cascade structure to meet multistandard radio communication specifications for a wide-band RF receiver. A filtering cascade composed of a 5th order Comb filter, a half-band filter and a FIR selector filter is proposed. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators definitions. Some experimental results are given to evaluate designed FPGA-based decimating filter circuit.