Design and implementation of a general-purpose processor for space systems

Author

Perschy, James A.

Author_Institution

Appl. Phys. Lab., Johns Hopkins Univ., Laurel, MD, USA

Volume

2

fYear

1999

fDate

6/21/1905 12:00:00 AM

Abstract

The requirements for this processor were established using the experience of the hardware and software designers in the APL Space Department. The use of commercial hardware and software products, combined with an error- and fault-tolerant architecture, resulted in a low-cost design without adversely affecting overall reliability. The processor´s architecture and mechanical design, and hardware and software test and validation methods are described

Keywords

aerospace computing; avionics; fault tolerant computing; microprocessor chips; reduced instruction set computing; space vehicle electronics; system buses; MIL-STD-1553 interface; PCI bus; RISC MIPS architecture; TIMED spacecraft; bus protocol circuit; commercial products; design requirements; error-tolerant architecture; fault-tolerant architecture; flight computer; general-purpose processor; hardware test; implementation; low-cost design; mechanical design; software test; space systems; Computer architecture; Connectors; Error correction; Flash memory; Global Positioning System; Hardware; Process design; Random access memory; Software design; Space vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Avionics Systems Conference, 1999. Proceedings. 18th

Conference_Location

St Louis, MO

Print_ISBN

0-7803-5749-3

Type

conf

DOI

10.1109/DASC.1999.821998

Filename

821998