Very high speed circuits layout design with automated parasitic symmetrization

In this paper, we discuss on Very High Speed Integrated Circuits design. In such circuits layout design, propagation and parasitic influence have to be taken into account. Symmetrical design is a good way to minimise propagation discrepancies, parasitic effects and in consequence reach the circuit speed limits. Starting from designers´ needs for such designs, a method was developed to extract circuit symmetries from an electrical scheme. A tool based on this method is discussed. Its vocation is to perform initial symmetrical placement and to preserve circuit´s symmetries during full-custom layout design