Title :
Influence of thermal annealing on the deformation of Cu-filled TSV
Author :
Hongwen He ; Xiangmeng Jing ; Liqiang Cao ; Daquan Yu ; Kai Xue ; Wenqi Zhang
Author_Institution :
Nat. Center for Adv. Packaging, Wuxi, China
Abstract :
Through silicon via (TSV) is regarded as one of the most advanced packaging technologies, however, many serious reliability issues need to be paid more concerns. The Cu pumping effect is one of the most crucial reliability problems. Due to different coefficient of thermal expansion for different packaging materials, Cu-TSV can deform and damage the wiring redistribution layers and degrade the reliability of the package as a whole during normal processing. Therefore, this work focuses on the influence which different thermal annealing processes have on Cu pumping in Cu-filled TSVs. Cu TSVs having 20μm in diameter and 120μm in depth were fabricated on 200 mm wafers by etching, insulation layer deposition, barrier layer deposition, seed layer deposition and Cu plating in sequence. Then the wafer surface was polished to remove the excessive Cu. Two anneal approaches were designed to investigate Cu TSV pumping. One was CMP first before annealing, and the other was annealing before CMP and followed by the 2nd annealing. Anneal tests were done in a nitrogen environment to protect Cu from oxidation. The annealing temperatures were set at 300°C and 400°C with a dwell time of 40min. The degree of pumping was evaluated by measuring the height and volume profiles before and after annealing by using a white light interferometer. Results show that the Cu TSV increased by 0.105μm and 0.168μm in height and 90.443μm3 and 93.993μm3 in volume at 300°C and 400°C with CMP first approach. However, the Cu TSV increased by only 0.066μm and 0.075μm and 30.797μm3 and 10.077μm3 in volume at 300°C and 400°C with anneal first approach. It can be concluded that the Cu pumping effect may be restrained by anneal first approach.
Keywords :
annealing; etching; integrated circuit packaging; integrated circuit reliability; light interferometers; pumps; three-dimensional integrated circuits; CMP; Cu; TSV deformation; anneal first approach; barrier layer deposition; etching; height profiles; insulation layer deposition; package reliability; packaging materials; plating; pumping effect; seed layer deposition; size 20 mum; size 200 mm; temperature 300 degC; temperature 400 degC; thermal annealing processes; thermal expansion; through silicon via; time 40 min; volume profiles; white light interferometer; wiring redistribution layers; Annealing; Morphology; Optical interferometry; Reliability; Silicon; Surface treatment; Through-silicon vias;
Conference_Titel :
Electronics System-Integration Technology Conference (ESTC), 2014
Conference_Location :
Helsinki
DOI :
10.1109/ESTC.2014.6962763