DocumentCode :
1600767
Title :
Structured LDPC over urn model channels with memory
Author :
Nagarajan, Vijay ; Milenkovic, Olgica
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
Volume :
1
fYear :
2004
Firstpage :
543
Abstract :
In this paper we investigate the performance of structured LDPC codes over a class of channels with memory. The channels under consideration are based on Polya´s urn model (F.Alajaji et al, IEEE Trans. Inform. Theory, vol.40, no.6, p.2035-2041, 1994) and can be viewed as a practical representative of channels with burst errors. The BER curves for iterative decoding with channel estimation show that random-like codes and a new class of regular and irregular codes, based on parity-check matrices of the form of block-circulants, have comparable performance for codelengths of the order of several thousands. Furthermore, the complete convergence region within the parameter space of the urn channel model is determined by using a new technique for generating side-information, termed state XORing. This technique also allows for complete characterization of the convergence region of another important bursty channel model, namely the Gilbert-Eliot scheme. Some possible applications of the results described in this paper are for designing reliable coding schemes for communication over fading or storage channels.
Keywords :
block codes; channel estimation; convergence; error statistics; fading channels; iterative decoding; parity check codes; random codes; Gilbert-Eliot scheme; Polya urn model channels; bit error rate curves; block-circulants; burst errors; bursty channels; channel estimation; channels with memory; fading channels; irregular codes; iterative decoding; parameter space convergence region; parity-check matrices; random-like codes; regular codes; side-information generation; state XORing; storage channels; structured LDPC codes; Bit error rate; Channel estimation; Convergence; Fading; Frequency shift keying; Hardware; Iterative algorithms; Iterative decoding; Memoryless systems; Parity check codes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering, 2004. Canadian Conference on
ISSN :
0840-7789
Print_ISBN :
0-7803-8253-6
Type :
conf
DOI :
10.1109/CCECE.2004.1345094
Filename :
1345094
Link To Document :
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