NEM relay based memory architectures for low power design

Nano-electromechanical (NEM) relays are a promising class of emerging devices that exhibit zero leakage operation. This work proposes three new NEM relay based parallel readout memory bitcell architectures that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. Accurate Verilog-A models were developed based on published fabrication results of NEM relays operating at 1V with a nominal air gap of 5 - 10nm. Bitcell stability and access time analysis are performed for all the proposed architectures and the results are presented.