DocumentCode
1602274
Title
Selecting a well distributed hard case test suite for IEEE standard floating point division
Author
McFearin, Lee D. ; Matula, David W.
Author_Institution
Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
89
Lastpage
96
Abstract
We investigate two sets of hard to round p×p bit fractions arising from division of a normalized p bit floating point dividend by a normalized p bit floating point divisor. These sets can be characterized by the p×p bit fraction\´s quotient bit string, beginning with or just after the round bit, having the maximum number (p-1) of repeating like bits, specifically 00...01 or 11:..10 for the directed rounding "RD-hard" set and 100...01 or 011...10 for the round-to-nearest "RN-hard" set. We describe an algorithm for generating both the RD-hard and RN-hard sets in order of quotient value for any p, and use properties of fractions and continued fractions to characterize the distribution of these sets based on numerator, denominator, and quotient values. As a practical chip test example we summarize test runs showing our hard to round test suites are several orders of magnitude more efficient than random testing in finding erroneous quotients computed by the 1993 Pentium Processor having the well known fdiv flaw
Keywords
IEEE standards; floating point arithmetic; logic testing; IEEE standard; floating point division; hard to round test; quotient value; random testing; Algorithm design and analysis; Arithmetic; Character generation; Chip scale packaging; Computer aided software engineering; Computer science; Hardware; Iterative algorithms; Table lookup; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-7695-1200-3
Type
conf
DOI
10.1109/ICCD.2001.955008
Filename
955008
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