Title :
Design of nanoelectronic ICs: Noise-tolerant logic based on cyclic BDD
Author :
Yanushkevich, S.N. ; Tangim, G. ; Kasai, S. ; Lyshevski, S.E. ; Shmerko, V.P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada
Abstract :
This paper reports new and practical design schemes for nanoscale integrated circuits, in order to ensure their functionality despite noise and faults. The proposed designs use a new cyclic binary decision diagram (BDD). The cyclic BDD enables the conventional BDD design algorithms by using feedback and Markov Random Field (MRF) model of logic gates. By applying the feedback and MRF premises, effective and robust design can be achieved. Simulations are reported to justify the fault-tolerance and noise-immunity of the proposed schemes.
Keywords :
Markov processes; binary decision diagrams; fault tolerance; integrated circuit design; logic circuits; logic design; logic gates; nanoelectronics; Markov random field; binary decision diagram; cyclic BDD; fault tolerance; feedback model; logic gates; nanoelectronic IC; nanoscale integrated circuits; noise immunity; noise-tolerant logic; Bit error rate; Boolean functions; Data structures; Integrated circuit modeling; Logic gates; Semiconductor device modeling; Signal to noise ratio;
Conference_Titel :
Nanotechnology (IEEE-NANO), 2012 12th IEEE Conference on
Conference_Location :
Birmingham
Print_ISBN :
978-1-4673-2198-3
DOI :
10.1109/NANO.2012.6322133
